The present invention generally relates to address transition detector circuits, and more particularly to an address transition detector circuit which detects a transition of an address signal and outputs a detection signal which is indicative of the address transition.
The address transition detector circuit detects a transition of an address which is supplied to a memory circuit and outputs a detection signal which is indicative of the address transition. This detection signal is used to set the level of bit lines or word lines to an intermediate level so that the level of the bit line or word line changes to a level which is in correspondence with a next address within a short time. Accordingly, it is important that the address transition detector circuit outputs the detection signal quickly when the address transition is detected.
FIG. 1 shows an example of a conventional address transition detector circuit. In FIG. 1, A0 through An denote n+1 address signal bits which are respectively obtained by once inverting address signal bits A0 through An of the address signal, and A0 through An denote n+1 address signal bits which are respectively obtained by twice inverting the address signal bits A0 through An of the address signal. The address signal bits Ai and Ai are supplied to a corresponding detection circuit 1.sub.i, where i=0, 1, . . . , n.
Because the circuit constructions of the detection circuits 1.sub.0 through 1.sub.n are the same, a description will only be given of the circuit construction and operation of the detection circuit 1.sub.0. The detection circuit 1.sub.0 comprises NAND circuits 2 and 3, loads Z1 and Z2, and n-channel metal oxide semiconductor field effect transistors (MOSFETs) Tr1 and Tr2 which are connected as shown.
When the address signal bit A0 has a high level and the address signal bit A0 has a low level, the NAND circuit 3 outputs a high-level signal and the two input signals to the NAND circuit 2 both have high levels. Hence, the NAND circuit 2 outputs a low-level signal. The output signals of the NAND circuits 2 and 3 are respectively applied to the transistors Tr1 and Tr2, and thus, the transistor Tr1 turns OFF and the transistor Tr2 turns ON.
When the address signal bit A0 changes to a low level and the address signal bit A0 changes to a high level, a first input signal to the NAND circuit 2, that is, the address signal bit A0, has the low level. For this reason, the output signal level of the NAND circuit 2 immediately becomes high regardless of a second input signal to the NAND circuit 2, that is, independently of the output signal of the NAND circuit 3. On the other hand, a first input signal to the NAND circuit 3 has a high level because it is the address signal bit A0. Hence, the output signal level of the NAND circuit 3 is determined by a second input signal thereto, that is, the level of the output signal of the NAND circuit 2 which is supplied to the NAND circuit 3. As mentioned above, the output signal of the NAND circuit 2 immediately changes from the low level to the high level, but the output signal of the NAND circuit 2 is supplied to the NAND circuit 3 via the load Z1. As a result, the second input signal to the NAND circuit 3 gradually rises from the low level to the high level with a time constant which is determined by the load Z1 and a stray capacitance of an input terminal of the NAND circuit 3 which receives the second input signal.
Therefore, the output signal of the NAND circuit 3 remains at the high level for a predetermined time starting from a time when the output signal of the NAND circuit 2 changes to the high level until a time when a threshold value of the NAND circuit 3 is exceeded. The output signal of the NAND circuit 3 changes to the low level only after the predetermined time elapses.
During the above mentioned predetermined time, the transistors Tr1 and Tr2 are both ON and a current flows in a current path which is made up of a pull-up load Z5, the transistor Tr1 and the transistor Tr2. Consequently, the potential becomes a low level at a common node NP which connects the load Z5, a drain of the transistor Tr1 and an input terminal of an inverter 5.
After the predetermined time elapses, the transistor Tr1 remains in the ON state but the transistor Tr2 changes from the ON state to the OFF state. Thus, the aforementioned current no longer flows in the current path and the potential at the common node NP becomes the high level similarly to the case where the address signal bit A0 has the high level and the address signal bit A0 has the low level. Accordingly, a transition detection signal which is obtained from the inverter 5 is a positive polarity pulse which has a high level for a predetermined time when the address signal bit A0 (A0, A0) undergoes a transition.
The other detection circuits 1.sub.1 through 1.sub.n operate similarly to the detection circuit 1.sub.0. Therefore, when at least one of the address signal bits A0 through An undergoes a transition, the positive polarity pulse which has the high level for the predetermined time is output from the inverter 5 as the transition detection signal.
However, according to the conventional address transition detector circuit, the n+1 detection circuits 1.sub.0 through 1.sub.n are coupled in parallel and the outputs of these detection circuits 1.sub.0 through 1.sub.n are coupled in common to the load Z5. For this reason, there is a large stray capacitance in an interconnection L between the load Z5 and the outputs of the detection circuits 1.sub.0 through 1.sub.n. Because of this large stray capacitance of the interconnection L, the potential at the common node NP cannot undergo a rapid change and can only change with a certain inclination, thereby introducing a delay when the potential at the common node NP falls. The conventional address transition detector circuit thus suffers a problem in that the rise of the transition detection signal output from the inverter 5 is slow, that is, the transition detection timing is slow.
On the other hand, it is possible to make the potential change at the common node NP quick by increasing the size of the transistors Tr1 and Tr2. But in this case, it is necessary to also make the size of the circuit which drives the transistors Tr1 and Tr2 large. As a result, the conventional address transition detector circuit becomes bulky due to the large transistors Tr1 and Tr2 and the large driving circuit which occupy a large space.